The subject matter disclosed herein relates generally to integrated circuit devices, and more particularly, to three-dimensional stacked integrated circuit devices including an interposer.
In conventional three-dimensional (3D) stacked integrated circuit (IC) packaging, semiconductor devices are stacked and interconnected to each other vertically, enabling a smaller IC package size and facilitating increased electrical performance (e.g., increased bandwidth, reduced power consumption, etc.). At least some known 3D stacked IC devices include a memory device—or a memory stack—that is placed on top of a logic device due to the increased number of interconnects of the logic device that need to connect to external circuitry. Typically, logic devices, however, have increased power dissipation, and therefore, increased operating temperatures, in comparison to the memory devices. Thus, with at least some 3D stacked IC devices it is not a thermally advantageous arrangement to position the logic device between the memory device and a substrate of the 3D stacked IC devices.
In addition, at least some known 3D stacked IC devices include through silicon vias (TSVs) formed in the logic device to facilitate electrically connecting the memory device to the external circuitry, which adds complexity and cost to the manufacturing of the logic device. In at least some known 3D stacked IC devices, the number of interconnects between the logic device and the memory and external circuitry would require an increase in the number of TSVs in the memory device, thereby reducing the efficient use and cost effectiveness of the memory device real estate.